VLIW Operation Refinement for Reducing Energy Consumption

The demand for mobile computer power has exploded in the recent years. Variable length VLIW processors offer the necessary performance at low power. Software optimizations are necessary to further decrease the energy consumption. In this article we present a compiler optimization which reduces the dynamic power dissipation resulting from the switching activities during instruction fetch. Energy consumption can be reduced by minimizing the Hamming distance between successively fetched instruction words. Using a dynamic programming approach we first compute a set of optimal instruction arrangements of the execution bundles in a basic block. These sets are used in an enumerative optimal algorithm and a genetic evolution, in order to minimize an objective function for the global Hamming distance. We evaluated our algorithms on different variable length VLIW architectures with 3 to 6 parallel functional units. On a large set of DSP benchmark programs the Hamming distance can be reduced by about 10% on average. Maximum reductions range up to 30%.